In logic electronic circuits, in particular those produced in the CMOS technology, it is known that the average electrical power consumed varies approximately with the square of the power supply voltage of the electronic circuit, while the information propagation time (and thus the time necessary to execute a given operation) is approximately inversely proportional to that power supply voltage.
It is therefore possible to reduce the energy consumed for a given operation (equal to the product of the power consumed and the time necessary for the operation) by reducing the power supply voltage, if the function involved makes a compromise on the speed of execution of the operation possible, of course.
In this context, it has been proposed, for example in the papers “An LSI for Vdd-Hopping and MPEG4 System Based on the Chip”, in the proceedings of the IEEE Intl. Symp. on Circuits and Systems (ISCAS), 2001, and “Fast Block-Wise Vdd-Hopping Scheme”, in the proceedings of the IEICE Society Conference, 2003, to select the power supply voltage as either a high voltage for operation of the electronic circuit under a nominal regime (short operation execution times) or a low voltage for low power consumption.
In such systems, problems arise during phases of transition between the high and low voltages, for example because of injection of current from the high-voltage supply to the low-voltage supply if the two voltages are applied simultaneously to prevent any interruption in power supply.